Ask me what winning looks like, and I don’t start with tapeout. Winning means our customers stop thinking about execution risk when they work with us.
In our industry, tapeouts often get the celebration. The mask set releases, the team gathers, and someone brings in cake and congratulatory emails fly. I understand why because it’s a real milestone, and we intend to keep earning it. But I’ve never measured a program by that moment. I measure it by what happens after. By this, I mean how the silicon, the package, and the test program come together at bringup and at volume, and this happens months and quarters after the tapeout party is over. That’s the stretch of the process I’ve spent 25+ years of my career on, which spans across production shipments on nodes from microns to 3nm. And this is the conviction shaping how we’re building at TYLsemi, across our chiplets and our full custom silicon XPU programs.
Tapeout is where you stop being able to change things cheaply
Tapeout is the moment a design meets silicon reality. Treating it like it is the finish line or a handoff is one of the more expensive mistakes a silicon program can make.
On a recent XPU program I oversaw, we had a hard-fought tapeout and first silicon came back functional. The temptation in that moment is always to declare victory. What actually consumed the next several months was debugging an obscure design marginality that only showed up in long-term device reliability testing. It was the slow, unglamorous work of characterization across corners, understanding the interaction between the die and the package, maturing the test program on ATE, and running down every finding until it was fully resolved. That work, not the tapeout itself, is what got us to volume shipments of a very successful product for a tier-1 customer and it was millions of units strong.
Our industry exists to manufacture and ship at volume with very low defects. Making sure every defect is accounted for, and every marginality is understood and solved, is what lets us commit to an aggressive ramp and stand behind product warranties for years to come.
How I know a design has actually landed
Success isn’t a single number I check off. It’s a sequence I watch and choreograph.
Early on, it’s bring-up where we see how much of the intended functionality comes up on the first pass, and how closely the measured parametrics track what we simulated. A design that matches its model is a design one can predict. A design that surprises you at bring-up will surely surprise you again at volume.
Then it becomes statistical. I want to see the yield learning curve bending in the right direction across successive lots, going beyond one good wafer. I want Cpk/Z statistics on the specs that matter to the customer’s design margin, and defect density trending down with known causes identified. Qualification is the next gate where reliability stress is completed to the standard the end market demands, and beyond.
The signal I trust most comes after all of that with a second and third production lot that behave like the first. It needs to include yields that correlate to a mathematical model and follow the trends in the pilot lots, low DPPM in the field, and a customer who reorders without asking us to re-prove anything. Shipping at volume, repeatably, with the data to explain why it works is the definition of success I hold my team to.
Nobody builds silicon alone
Creating silicon takes a village — an international one, spanning foundries, EDA and IP suppliers, OSATs, test, hardware, architects, and engineers across many companies. Anyone who thinks otherwise hasn’t been through a real silicon shipment.
A data center program we ran is the clearest example I can point to explain this. Thermal constraints meant we had to work across silicon fabrication, package design, and test hardware suppliers, and align with our EDA tool vendors to make sure our thermal budgets were understood and designed for across silicon, package, and test. This was all done together, not in sequence. Day to day, that partnership looked deliberately formal with a shared tracker, joint reviews, regular status updates, and the occasional urgent call or on-site visit. We stayed ready for everything and even kept a backup for the backup. What saved that product and its schedule wasn’t one hero or one technical expert. It was the team of engineers, the foundry team, our EDA and OSAT partners who were all working off the same data and solving the same problems.
You can’t instruct a team into this mindset
You have to build shared incentives. At TYLsemi, that shows up in a few concrete ways.
Post-silicon plans are part of our program plans from day one. Silicon, test, and product engineering are in the room early and often during design, because how we screen, test, and validate is part of how we design. We run a “bad news travels early” norm where raising a risk early is good judgment, and the only unacceptable outcome is a problem that was known and not shared. No program clears tapeout sign-off without a post-silicon readiness review. The bring-up, characterization, test, and qualification plan has to be on the table before we release the mask set, not improvised after first silicon comes back. We run honest post-silicon retrospectives on every program, including the ones that went well, and write down what we’d do differently.
We treat our foundry, packaging, and IP partners as part of our execution team, with shared roadmaps, early visibility into our pipeline, and joint reviews on schedule instead of escalation calls. That ecosystem posture is a large part of how a company our size delivers with the discipline of a much bigger one.
Why my engineering background still shapes how I run operations
Coming up through engineering changes how I think about operations because the silicon we build isn’t simply logistics. It’s where design intent becomes real and understanding that intent makes all the difference. Any chip schedule is a hypothesis about physics, tooling, resources, budget, and time. I can usually tell the difference between a date that’s aggressive and a date that’s mathematically possible, and I know which assumptions and risks to ask about. Being confident helps in a design review and being pragmatic is what helps you ship.
The bigger impact of an engineering background in operations, though, is communication using the same language. Being able to talk credibly with the design community, 3rd party IP and EDA partners, and customers, and to connect design challenges to schedule and production quality makes hard conversations possible. As co-founders of TYLsemi, my partners and I are building the same engineering-first, production mindset into our chiplet portfolio and into how we support customer’s silicon programs with heterogeneous integration and advanced packaging.
The same philosophy, different failure modes
The execution philosophy doesn’t change across our portfolio. What changes is where the risk lives.
With TYL.Connect and TYL.Power chiplets, design risk is lower for our customers because they’re building with the silicon we’ve already proven. This means a meaningful part of their design is production ready before their program even starts. The failure modes and the hard problems now shift to the boundaries. Interface compliance, known-good-die (KGD) test coverage, assembly and packaging yield, and thermal and power delivery behavior once several chiplets share a substrate. A chiplet that passes on its own and fails in an integrated package is a system problem we have to solve, which is why we invest heavily in die-level screening and in modeling the assembled system, and work with customers early to validate the reusable chiplet model.
On a custom silicon XPU program using our TYL.Forge platform, the risk concentrates differently. There’s far more under our control. The mask sets, package, substrate, system design and control concentrate execution risk. We have one shot at the mask set, one shot to get to production, for us and for the customer. This means freezing the specification, managing feature creep, holding schedule, controlling engineering and BOM costs, and staying engaged with the manufacturing and ecosystem partners through the full lifecycle to end of life.
Put simply, the mindset is the same for both. Only the risks and dependencies differ.
The standard I hold the team to
Many successful deliveries, across chiplets and custom silicon programs, on different nodes, for different end markets, are how we build a platform. And a platform is what a customer buys into when they trust us with their silicon roadmap. That’s what we’re building at TYLsemi.
Tapeouts will still get the celebration, and we intend to keep earning them. But we would rather be measured on the silicon we shipped and the customers who came back without asking us to prove it again.