The chiplet era is a collective build, always the work of more than one company. It rests on a shared set of rules: how die talk to die, how power gets delivered across a package, and how accelerators plug into the rest of the system. Get those rules right, collectively, and multi-die design goes from a one-off engineering feat to a repeatable path to silicon. Get them wrong, or leave them fragmented, and every team ends up re-solving the same integration problems on their own dime.
That’s the premise behind a set of announcements we’re making today: TYLsemi has joined the UCIe Consortium, PCI-SIG, the Open Compute Project (OCP), and the CXL Consortium. Individually, each membership connects a piece of our roadmap to the standard it depends on. Together, they say something bigger about how we intend to build: as a full participant inside the open ecosystem that makes chiplet-based AI infrastructure possible at scale, rather than a bystander watching from outside it.
Why These Four Organizations
UCIe Consortium. UCIe (Universal Chiplet Interconnect Express) is the de facto open standard for die-to-die interconnect, backed by 120+ members including Amkor, ASE, Google Cloud, Intel Meta, Nvidia, TSMC. It’s also the single most consequential standard for our roadmap: TYL.IO products are built to interoperate over UCIe, and a chiplet limited to a proprietary interconnect language stays a science project rather than a merchant chiplet. Joining UCIe puts us at the table as the spec evolves, rather than reacting to it after the fact.
PCI-SIG. PCIe remains the connectivity backbone for accelerators, storage, and host-to-device links across nearly every AI system in production today. TYL.IO family of products support PCIe Gen7, so PCI-SIG membership gives us direct visibility into where the spec is heading and a formal channel to help shape it: the same channel our customers’ own architects rely on.
Open Compute Project. OCP is where hyperscalers and infrastructure vendors set the practical, deployment-level standards for what actually ships in data centers. For a chiplet company selling into AI infrastructure, that audience overlap is direct: OCP membership puts TYLsemi in the room with the architects who will ultimately decide what a production-ready chiplet needs to look like at rack and fleet scale.
CXL Consortium. As accelerators take on more of the workload in AI and ML systems, the interconnect problem stops being just “chip to chip” and becomes “memory and compute working coherently across the system.” CXL is the open standard addressing that, and it’s increasingly relevant to how our power and IO chiplets fit into heterogeneous, accelerator-rich architectures. Getting ahead of that shift now is deliberate.
Standards Work Has Long Been How We Operate
Before TYLsemi, and continuing alongside it, I’ve served on the technical program committees that review the research shaping this industry, including the ISCA Industry Track, DAC, ISLPED, ISQED, and ISVLSI. ISQED alone has had me on the committee for eight consecutive years, from 2019 through the upcoming 2026 event.
That work is unglamorous: reviewing submissions, debating what belongs in a program, holding a bar for what counts as real contribution. But it’s also where you develop a feel for where the field is actually headed versus where the marketing decks say it’s headed. TYLsemi joining UCIe, PCI-SIG, OCP, and CXL is a continuation of that same instinct at the company level: show up, do the unglamorous work of building and reviewing the standard, and let that participation inform what we build rather than bolting standards compliance on at the end.
It’s also consistent with how TYLsemi approaches everything else. We aim to be a merchant partner across the ecosystem, rather than a captive supplier to one hyperscaler or a one-off design-services shop. We’re building standards-based, production-ready chiplets: TYL.IO for high-performance connectivity, TYL.Power for in-package power delivery, TYL.Scale for open scale-up interconnect, specifically so customers can integrate proven silicon into their own designs while leaving our supply chain risk and roadmap dependencies behind. Standards membership is the mechanism that keeps that promise credible. A chiplet that’s “standards-based” only means something if the company behind it holds an actual seat and a vote inside the standards body.
What This Means If You’re Architecting Multi-Die Systems
If you’re a system or SoC architect wrestling with the monolithic-to-chiplet transition, the practical takeaway is this: TYLsemi’s roadmap gets built with direct visibility into where UCIe, PCIe, OCP, and CXL are heading, by a team that’s spent years in the peer-review trenches of the broader semiconductor research community, rather than in isolation with the spec reconciled later. That should reduce your integration risk as much as ours. The whole point of a shared standard is that neither of us has to guess what the other side is going to do.
We’re at an inflection point where the industry either converges on a small set of open interconnect and power standards, or fragments into vendor-specific dead ends that recreate the exact integration burden chiplets were supposed to eliminate. TYLsemi intends to be squarely on the side of convergence, with a chiplet portfolio built by the people who helped shape the very standards it stays compatible with.
If you’re evaluating chiplet and custom silicon partners for your next-generation AI infrastructure and want to talk through how TYLsemi products and solutions fit into your architecture, reach out to our team. We’d welcome the conversation.