Rack-scale AI
Infrastructure silicon

Chiplets for connectivity, power, and efficiency, with seamless migration to full custom silicon.
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The TYLsemi portfolio

TYLsemi™ delivers production-ready chiplets for the core functions of AI infrastructure, plus custom silicon development for complete system solutions.
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TYL.IO™:
Versatile Connectivity

High-performance connectivity — first in the IO connectivity chiplet family

  • Enables high-bandwidth, low-latency data movement.
  • Built on PCIe and CXL standards.
  • Simplifies compute and IO disaggregation.
  • Reusable across multiple system design points.
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TYL.Power™:
Intelligent IVR

Efficient power delivery for XPUs

  • Delivers multi-domain power for compute, IO, and memory.
  • Enables intelligent control and
real-time optimization.
  • Improves system-level efficiency and performance.
  • Reduces board-level complexity and external components.
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TYL.ForgeSM:
Custom Silicon

End-to-end silicon delivery, built on chiplets

  • Delivers full custom silicon for complex AI systems.
  • Integrates design, packaging, and 
 manufacturing.
  • Reduces integration risk and development overhead.
  • Enables scalable, production-ready 
 system deployment.
  • Up to 50% reduction in development time and cost, for faster time to 
 market.

Products and solutions

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TYL.IO

High-performance connectivity for scalable AI systems

The TYL.IO chiplet is the first in the TYLsemi family of connectivity chiplets, delivering latest generation PCIe and CXL-based high-bandwidth, low-latency connectivity across multi-die systems. It enables efficient communications between compute, memory, and networking elements, establishing a reusable foundation for system-level data movement, with additional chiplets extending coverage to further interconnect standards and application domains.

As AI architectures shift to chiplet-based designs, given analog and IO devices are not scaling with process nodes, IO connectivity becomes a critical bottleneck for performance, power efficiency, and system integration.

The TYL.IO chiplet addresses this with a standards-based, production-ready solution that removes the need to design and validate IO connectivity for every program. With an IO chiplet-based design, customers can upgrade IO connectivity independent of their existing compute silicon, enabling newer PCIe generations without a full redesign and reducing networking overhead across the rack.

Features


  • PCIe and CXL-based connectivity for chiplet and system-level communications.
  • High-bandwidth, low-latency data movement across compute, memory, and IO domains.
  • Reusable IO architecture that reduces engineering effort across AI designs.
  • Flexible die-to-die and package-level integration.
  • Production-ready silicon aligned to real system constraints.
TYL.IO diagram
Block diagram of a disaggregated XPU with TYL.IO die providing connectivity layer to compute die.
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TYL.Power

Efficient, intelligent power delivery for multi-die systems

The TYL.Power chiplet is an integrated voltage regulator (IVR) chiplet that delivers multi-domain, in-package power management for AI systems. It provides tightly coupled power delivery for compute, improving efficiency while enabling more dynamic system control.

As power density and system complexity increase, traditional board-level power delivery becomes inefficient and difficult to scale. The TYL.Power chiplet moves power management closer to the silicon, enabling faster response, finer control, and improved overall system performance.

Features

  • In-package voltage regulation for improved efficiency and performance.
  • Reduced board-level complexity and external power components.
  • Real-time control and feedback for dynamic system optimization.
  • Production-ready silicon for demanding AI workloads.
TYL.Power diagram
Expanded package diagram illustrating TYL.Power integrating closed loop intelligent in-package power delivery.
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TYL.Forge

End-to-end silicon delivery for complex AI systems

The TYL.Forge platform is an end-to-end silicon platform that delivers full custom AI infrastructure systems by integrating chiplets, IP, packaging, and manufacturing into a single, production-ready deliverable. It combines reusable chiplet building blocks with system-level design and ecosystem coordination to enable complete silicon deployment.

Unlike traditional approaches that rely on fragmented IP blocks, tools, and design services, the TYL.Forge platform provides a unified model for building and deploying complex multi-die systems. It is intended for high-volume silicon production with reduced risk and greater predictability.

Features


  • Full custom silicon built using production-ready chiplets.
  • Integration of IP, chiplets, packaging, and manufacturing.
  • Coordinated execution across foundry and OSAT ecosystems.
  • Reduced integration risk and development overhead.
  • Production-ready systems for high-volume deployment.
  • Up to 50% reduction in development time and cost.
TYL.Forge chevron
An end-to-end flow showing the TYL.Forge platform's unified path from silicon design to production-ready delivery — foundry, OSAT, and supply chain in a single platform.
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TYL.Mem™

Versatile memory connectivity product family for AI systems

A planned product family focused on memory connectivity for advanced AI systems, with additional details to be announced as the roadmap progresses.

Designing your next AI system?

Talk to our silicon engineers and build faster with proven, production-ready chiplets.

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