The market for AI silicon is exploding, with analysts estimating this growth to be in the $600+ billion range and that number keeps rising. Applications such as agentic AI need more compute power, and while one might think that’s the main bottleneck, the real roadblock is getting these chips developed. Let’s face it…chip development is risky, complex, costly, and always takes longer than projected.
What if you could build AI silicon the way you build software — assembling proven, standardized components instead of engineering every key function from scratch? That’s what TYLsemi™ makes possible. Our chiplets are pre-built, validated, production-ready blocks you can pick, combine, and drop into your design. The result: AI infrastructure silicon developed in nearly half the time and at half the cost, with minimal risk and a full ecosystem already in place for high-volume manufacturing.
Why chiplets and why now?
Chiplets have long been considered the holy-grail of AI silicon development. However, only in recent years have advancements in the industry been achieved to pave the way for their full potential. We needed standards to provide a common language…and UCIe has emerged to fill that need. In the last 6 months to one year, the traction around UCIe has been incredible, ending the proprietary lock-in that limited the possibilities. Packaging technology has also taken a major leap forward. After years of incremental progress, the industry now has access to more advanced packaging technology than ever before, making chiplets the best solution for solving the AI infrastructure problem.
Even hyperscalers such as Meta have publicly adopted chiplet-based architectures for their AI accelerators, citing months-not-years upgrade cycles and per-die process node optimization. In a recent blog, Meta describes how they “achieve high velocity through a reusable and modular design across all levels: chiplets, chassis, racks, and network infrastructure.” They architected their accelerators as systems of chiplets — discrete, reusable building blocks for compute, I/O, and networking. Because each chiplet can be upgraded separately, they were able to implement improvements in months rather than years. They also describe how different chiplets can be manufactured at different process nodes that are most cost-effective while meeting performance and power requirements.
It’s no secret that when hyperscalers move, the industry moves. The standard has now been created, and the use of chiplets to create custom AI silicon is about to take off at lightning speed.
No one owns the chiplet platform layer
Many players participate in chiplets, but their offerings are either captive to in‑house designs or fragmented across IP and services vendors. For customers, this often feels like embarking on a full custom development—high cost, high risk—rather than leveraging a robust, pre‑built platform. The TYLsemi platform, aimed at the AI infrastructure space, is the first solution to offer a full portfolio across IO, power, and memory paired with a chiplet-based custom silicon design and supply-chain ownership. This standards-based, production-ready portfolio gives developers a faster, lower-risk path for developing AI silicon from architecture to deployment. An important side note—TYLsemi has the backing of TSMC, who agrees that there is a need for this in the market.
Solving the $10 billion power delivery problem
AI infrastructure silicon doesn’t just have a compute problem. It also has a power problem. The scale of energy demand from modern AI clusters is so acute that every major hyperscaler has signed nuclear deals, with over 9.8 GW of capacity committed across 13 announced projects as of 2026. That’s not an IT decision; that’s an energy policy decision. And it signals just how severe the power challenge has become.
But while the industry debates gigawatts at the grid level, the real problem is what happens at the last mile, inside the package itself. As AI SoCs grow more complex and multi-die systems pack more compute into smaller spaces, getting clean, efficient power to each die becomes one of the hardest engineering challenges in the stack. Traditional board-level power delivery simply can’t keep up.
This is exactly what the TYL.Power™ chiplet was built to solve. As an integrated voltage regulator (IVR) chiplet, TYL.Power sits directly in the package, where it can save up to 300W on a 2,000W XPU by delivering power that last mile directly to the die’s transistors. In addition, by moving voltage regulation into the package, it reduces board-level complexity, improves efficiency, and gives architects real-time control over power at the die level.
We are excited to bring TYLsemi out of stealth today to solve all the problems I described above. With chiplets available across connectivity, power, and memory, we have a full portfolio to usher in a new era of chip development. We also have the team to execute on our vision. Our founders have shipped more than 30 million chips, closed over $1B in orders, and completed more than 75 high-volume designs with first-pass success. We have a 15+ year relationship with TSMC and close alignment across OSATs and IP partners. That track record shapes how we build products and support customers.
You can check out our portfolio of products here, and our launch press release here. We are also hiring, so please visit our careers page. This is one of the most exciting times in the semiconductor industry. By fast-tracking silicon development, we believe we can help transform the entire landscape.